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21 lines
576 B
Systemverilog
21 lines
576 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// Simple bi-directional alias test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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initial begin
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int dict[string] = '{1, 2};
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int dict2[string] = '{3: 4}; // Legal due to value-to-string conversion
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$display("dict=%p", dict);
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$display("dict2=%p", dict2);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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