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23 lines
464 B
Systemverilog
23 lines
464 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk,
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input [7:0] d,
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input [2:0] a,
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output [7:0] q
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);
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always_ff @(posedge clk) tick(a);
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logic [7:0] d_ = d;
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logic [7:0] q_;
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assign q = q_;
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task automatic tick(logic [2:0] a);
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q_[a] <= d_[a];
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endtask
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endmodule
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