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79 lines
1.6 KiB
Systemverilog
79 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t(/*AUTOARG*/);
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int a;
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int b;
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int i;
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initial begin
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a = 10;
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i = (a = 2);
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`checkd(a, 2); `checkd(i, 2);
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a = 10;
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i = (a += 2);
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`checkd(a, 12); `checkd(i, 12);
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a = 10;
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i = (a -= 2);
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`checkd(a, 8); `checkd(i, 8);
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a = 10;
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i = (a *= 2);
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`checkd(a, 20); `checkd(i, 20);
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a = 10;
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i = (a /= 2);
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`checkd(a, 5); `checkd(i, 5);
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a = 11;
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i = (a %= 2);
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`checkd(a, 1); `checkd(i, 1);
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a = 10;
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i = (a &= 2);
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`checkd(a, 2); `checkd(i, 2);
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a = 8;
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i = (a |= 2);
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`checkd(a, 10); `checkd(i, 10);
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a = 10;
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i = (a ^= 2);
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`checkd(a, 8); `checkd(i, 8);
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a = 10;
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i = (a <<= 2);
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`checkd(a, 40); `checkd(i, 40);
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a = 10;
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i = (a >>= 2);
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`checkd(a, 2); `checkd(i, 2);
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a = 10;
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i = (a >>>= 2);
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`checkd(a, 2); `checkd(i, 2);
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a = 10;
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i = (a = (b = 5));
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`checkd(a, 5); `checkd(i, 5); `checkd(b, 5);
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a = 10;
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b = 6;
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i = ((a += (b += 1) + 1));
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`checkd(a, 18); `checkd(i, 18); `checkd(b, 7);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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