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39 lines
799 B
Systemverilog
39 lines
799 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc;
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bit valid;
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property prop;
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int prevcyc;
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(valid, prevcyc = cyc) |=> (cyc == prevcyc + 1);
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endproperty
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default clocking @(posedge clk); endclocking
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assert property(prop);
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property with_def(int nine = 9);
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cyc == 9 |-> cyc == nine;
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endproperty
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assert property(with_def);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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valid <= cyc == 5;
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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