mirror of
https://github.com/verilator/verilator.git
synced 2025-01-21 05:44:03 +00:00
16 lines
324 B
Systemverilog
16 lines
324 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2022 by Antmicro Ltd.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t (/*AUTOARG*/
|
|
clk
|
|
);
|
|
|
|
input clk;
|
|
|
|
labeled_imas: assert #1 (clk); // BAD: #1
|
|
|
|
endmodule
|