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75 lines
2.0 KiB
Systemverilog
75 lines
2.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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static function bit get_true();
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return 1'b1;
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endfunction
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static function bit test_find_index_in_class();
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if (get_true) begin
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int q[$] = {0, -1, 3, 1, 4, 1};
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int found_idx[$];
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found_idx = q.find_index(node) with (node == 1);
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return found_idx[0] == 3;
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end
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return 0;
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endfunction
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endclass
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module t (/*AUTOARG*/
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);
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function bit test_find;
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string bar[$];
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string found[$];
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bar.push_back("baz");
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bar.push_back("qux");
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found = bar.find(x) with (x == "baz");
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return found.size() == 1;
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endfunction
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function static bit test_find_index;
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int q[$] = {1, 2, 3, 4};
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int found[$] = q.find_index(x) with (x <= 2);
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return found.size() == 2;
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endfunction
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function static bit test_find_first_index;
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int q[] = {1, 2, 3, 4, 5, 6};
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int first_even_idx[$] = q.find_first_index(x) with (x % 2 == 0);
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return first_even_idx[0] == 1;
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endfunction
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function bit is_even(int a);
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return a % 2 == 0;
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endfunction
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function static bit test_find_first_index_by_func;
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int q[] = {1, 2, 3, 4, 5, 6};
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int first_even_idx[$] = q.find_first_index(x) with (is_even(x));
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return first_even_idx[0] == 1;
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endfunction
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function automatic bit test_sort;
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int q[] = {-5, 2, -3, 0, 4};
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q.sort(x) with (x >= 0 ? x : -x);
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return q[1] == 2;
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endfunction
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initial begin
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if (!test_find()) $stop;
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if (!test_find_index()) $stop;
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if (!test_find_first_index()) $stop;
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if (!test_find_first_index_by_func()) $stop;
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if (!test_sort()) $stop;
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if (!Cls::test_find_index_in_class()) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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