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172 lines
6.5 KiB
Systemverilog
172 lines
6.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Iztok Jeras.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// parameters for array sizes
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localparam WA = 4;
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localparam WB = 6;
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localparam WC = 8;
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// 2D packed arrays
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logic [WA+1:2] [WB+1:2] [WC+1:2] array_dsc; // descending range array
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/* verilator lint_off ASCRANGE */
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logic [2:WA+1] [2:WB+1] [2:WC+1] array_asc; // ascending range array
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/* verilator lint_on ASCRANGE */
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logic [1:0] array_unpk [3:2][1:0];
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integer cnt = 0;
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integer slc = 0; // slice type
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integer dim = 0; // dimension
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integer wdt = 0; // width
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initial begin
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`checkh($dimensions (array_unpk), 3);
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`ifndef VCS
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`checkh($unpacked_dimensions (array_unpk), 2); // IEEE 2009
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`endif
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`checkh($bits (array_unpk), 2*2*2);
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`checkh($low (array_unpk), 2);
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`checkh($high (array_unpk), 3);
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`checkh($left (array_unpk), 3);
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`checkh($right(array_unpk), 2);
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`checkh($increment(array_unpk), 1);
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`checkh($size (array_unpk), 2);
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end
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// event counter
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always @ (posedge clk) begin
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cnt <= cnt + 1;
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end
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// finish report
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always @ (posedge clk)
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if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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integer slc_next;
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// calculation of dimention sizes
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always @ (posedge clk) begin
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// slicing type counter
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case (cnt[3:2])
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2'd0 : begin slc_next = 0; end // full array
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2'd1 : begin slc_next = 1; end // single array element
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2'd2 : begin slc_next = 2; end // half array
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default: begin slc_next = 0; end
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endcase
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slc <= slc_next;
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// dimension counter
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case (cnt[1:0])
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2'd0 : begin dim <= 1; wdt <= (slc_next==1) ? WA/2 : (slc_next==2) ? WA/2 : WA; end
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2'd1 : begin dim <= 2; wdt <= WB; end
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2'd2 : begin dim <= 3; wdt <= WC; end
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default: begin dim <= 0; wdt <= 0; end
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endcase
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end
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt);
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`endif
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if (cnt[30:4]==1) begin
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// descending range
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if (slc==0) begin
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// full array
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`checkh($dimensions (array_dsc), 3);
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`checkh($bits (array_dsc), WA*WB*WC);
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if ((dim>=1)&&(dim<=3)) begin
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`checkh($left (array_dsc, dim), wdt+1);
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`checkh($right (array_dsc, dim), 2 );
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`checkh($low (array_dsc, dim), 2 );
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`checkh($high (array_dsc, dim), wdt+1);
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`checkh($increment (array_dsc, dim), 1 );
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`checkh($size (array_dsc, dim), wdt );
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end
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end else if (slc==1) begin
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// single array element
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`checkh($dimensions (array_dsc[2]), 2);
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`checkh($bits (array_dsc[2]), WB*WC);
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if ((dim>=2)&&(dim<=3)) begin
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`checkh($left (array_dsc[2], dim-1), wdt+1);
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`checkh($right (array_dsc[2], dim-1), 2 );
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`checkh($low (array_dsc[2], dim-1), 2 );
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`checkh($high (array_dsc[2], dim-1), wdt+1);
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`checkh($increment (array_dsc[2], dim-1), 1 );
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`checkh($size (array_dsc[2], dim-1), wdt );
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end
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`ifndef VERILATOR // Unsupported slices don't maintain size correctly
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end else if (slc==2) begin
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// half array
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`checkh($dimensions (array_dsc[WA/2+1:2]), 3);
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`checkh($bits (array_dsc[WA/2+1:2]), WA/2*WB*WC);
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if ((dim>=1)&&(dim<=3)) begin
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`checkh($left (array_dsc[WA/2+1:2], dim), wdt+1);
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`checkh($right (array_dsc[WA/2+1:2], dim), 2 );
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`checkh($low (array_dsc[WA/2+1:2], dim), 2 );
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`checkh($high (array_dsc[WA/2+1:2], dim), wdt+1);
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`checkh($increment (array_dsc[WA/2+1:2], dim), 1 );
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`checkh($size (array_dsc[WA/2+1:2], dim), wdt);
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end
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`endif
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end
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end else if (cnt[30:4]==2) begin
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// ascending range
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if (slc==0) begin
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// full array
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`checkh($dimensions (array_asc), 3);
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`checkh($bits (array_asc), WA*WB*WC);
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if ((dim>=1)&&(dim<=3)) begin
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`checkh($left (array_asc, dim), 2 );
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`checkh($right (array_asc, dim), wdt+1);
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`checkh($low (array_asc, dim), 2 );
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`checkh($high (array_asc, dim), wdt+1);
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`checkh($increment (array_asc, dim), -1 );
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`checkh($size (array_asc, dim), wdt );
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end
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end else if (slc==1) begin
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// single array element
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`checkh($dimensions (array_asc[2]), 2);
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`checkh($bits (array_asc[2]), WB*WC);
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if ((dim>=2)&&(dim<=3)) begin
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`checkh($left (array_asc[2], dim-1), 2 );
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`checkh($right (array_asc[2], dim-1), wdt+1);
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`checkh($low (array_asc[2], dim-1), 2 );
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`checkh($high (array_asc[2], dim-1), wdt+1);
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`checkh($increment (array_asc[2], dim-1), -1 );
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`checkh($size (array_asc[2], dim-1), wdt );
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end
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`ifndef VERILATOR // Unsupported slices don't maintain size correctly
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end else if (slc==2) begin
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// half array
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`checkh($dimensions (array_asc[2:WA/2+1]), 3);
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`checkh($bits (array_asc[2:WA/2+1]), WA/2*WB*WC);
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if ((dim>=1)&&(dim<=3)) begin
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`checkh($left (array_asc[2:WA/2+1], dim), 2 );
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`checkh($right (array_asc[2:WA/2+1], dim), wdt+1);
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`checkh($low (array_asc[2:WA/2+1], dim), 2 );
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`checkh($high (array_asc[2:WA/2+1], dim), wdt+1);
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`checkh($increment (array_asc[2:WA/2+1], dim), -1 );
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`checkh($size (array_asc[2:WA/2+1], dim), wdt );
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end
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`endif
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end
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end
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end
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endmodule
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