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36 lines
1.2 KiB
Systemverilog
36 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t (/*AUTOARG*/);
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initial begin
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int q[5];
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int qv[$]; // Value returns
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int qi[$]; // Index returns
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int i;
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string v;
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q = '{1, 2, 2, 4, 3};
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v = $sformatf("%p", q); `checks(v, "'{1, 2, 2, 4, 3} ");
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// Reduction methods
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i = q.sum with (item + 1); `checkh(i, 32'h11);
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i = q.product with (item + 1); `checkh(i, 32'h168);
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q = '{32'b1100, 32'b1010, 32'b1100, 32'b1010, 32'b1010};
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i = q.and with (item + 1); `checkh(i, 32'b1001);
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i = q.or with (item + 1); `checkh(i, 32'b1111);
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i = q.xor with (item + 1); `checkh(i, 32'hb);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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