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ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
108 lines
2.2 KiB
Verilog
108 lines
2.2 KiB
Verilog
// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t_blocking(/*AUTOARG*/
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// Outputs
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passed,
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// Inputs
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clk, reset_l
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);
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input clk;
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input reset_l;
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output passed; reg passed; initial passed = 0;
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integer _mode; initial _mode=0;
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reg [7:0] a;
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reg [7:0] b;
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reg [7:0] c;
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reg [7:0] mode_d1r;
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reg [7:0] mode_d2r;
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reg [7:0] mode_d3r;
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// surefire lint_off ITENST
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// surefire lint_off STMINI
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// surefire lint_off NBAJAM
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always @ (posedge clk or negedge reset_l) begin // filp-flops with asynchronous reset
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if (!reset_l) begin
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_mode <= 0;
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passed <= 0;
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end
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else begin
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_mode <= _mode + 1;
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if (_mode==0) begin
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$write("[%0t] t_blocking: Running\n", $time);
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a <= 8'd0;
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b <= 8'd0;
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c <= 8'd0;
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end
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else if (_mode==1) begin
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$write("[%0t] t_blocking: Running\n", $time);
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if (a !== 8'd0) $stop;
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if (b !== 8'd0) $stop;
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if (c !== 8'd0) $stop;
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a <= b;
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b <= 8'd1;
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c <= b;
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if (a !== 8'd0) $stop;
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if (b !== 8'd0) $stop;
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if (c !== 8'd0) $stop;
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end
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else if (_mode==2) begin
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$write("[%0t] t_blocking: Running\n", $time);
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if (a !== 8'd0) $stop;
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if (b !== 8'd1) $stop;
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if (c !== 8'd0) $stop;
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a <= b;
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b <= 8'd2;
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c <= b;
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if (a !== 8'd0) $stop;
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if (b !== 8'd1) $stop;
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if (c !== 8'd0) $stop;
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end
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else if (_mode==3) begin
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if (a !== 8'd1) $stop;
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if (b !== 8'd2) $stop;
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if (c !== 8'd1) $stop;
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end
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else if (_mode==4) begin
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if (mode_d3r != 8'd1) $stop;
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$write("[%0t] t_blocking: Passed\n", $time);
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passed <= 1'b1;
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end
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end
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end
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always @ (posedge clk) begin
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mode_d3r <= mode_d2r;
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mode_d2r <= mode_d1r;
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mode_d1r <= _mode[7:0];
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end
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reg [14:10] bits;
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// surefire lint_off SEQASS
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always @ (posedge clk) begin
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if (_mode==1) begin
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bits[14:13] <= 2'b11;
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bits[12] <= 1'b1;
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end
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if (_mode==2) begin
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bits[11:10] <= 2'b10;
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bits[13] <= 0;
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end
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if (_mode==3) begin
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if (bits !== 5'b10110) $stop;
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end
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end
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endmodule
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// Local Variables:
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// compile-command: "./vlint __FILE__"
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// End:
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