mirror of
https://github.com/verilator/verilator.git
synced 2025-01-07 15:17:36 +00:00
21 lines
914 B
Plaintext
21 lines
914 B
Plaintext
-V{t0,1}- Verilated::debug is on. Message prefix indicates {<thread>,<sequence_number>}.
|
|
-V{t0,2}+ Vt_verilated_debug::_ctor_var_reset
|
|
-V{t0,3}+++++TOP Evaluate Vt_verilated_debug::eval
|
|
-V{t0,4}+ Vt_verilated_debug::_eval_debug_assertions
|
|
-V{t0,5}+ Vt_verilated_debug::_eval_initial
|
|
-V{t0,6}+ Vt_verilated_debug::_eval_settle
|
|
-V{t0,7}+ Vt_verilated_debug::_eval
|
|
-V{t0,8}+ Vt_verilated_debug::_change_request
|
|
-V{t0,9}+ Clock loop
|
|
-V{t0,10}+ Vt_verilated_debug::_eval
|
|
-V{t0,11}+ Vt_verilated_debug::_change_request
|
|
-V{t0,12}+++++TOP Evaluate Vt_verilated_debug::eval
|
|
-V{t0,13}+ Vt_verilated_debug::_eval_debug_assertions
|
|
-V{t0,14}+ Clock loop
|
|
-V{t0,15}+ Vt_verilated_debug::_eval
|
|
-V{t0,16}+ Vt_verilated_debug::_sequent__TOP__1
|
|
*-* All Finished *-*
|
|
- t/t_verilated_debug.v:16: Verilog $finish
|
|
-V{t0,17}+ Vt_verilated_debug::_change_request
|
|
-V{t0,18}+ Vt_verilated_debug::final
|