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25 lines
557 B
Verilog
25 lines
557 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2018 by Wilson Snyder.
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// Make sure type errors aren't suppressable
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// verilator lint_off WIDTH
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module t(/*AUTOARG*/);
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task checkset(const ref int bad_const_set);
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bad_const_set = 32'h4567; // Bad setting const
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endtask
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task checkset2(ref int int_ref);
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endtask
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initial begin
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int i;
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byte bad_non_int;
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checkset(i);
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checkset2(bad_non_int); // Type mismatch
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end
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endmodule
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