verilator/test_regress/t/t_trace_cat_reopen_0100.out
2018-08-30 20:05:13 -04:00

241 lines
2.6 KiB
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$version Generated by VerilatedVcd $end
$date Thu Aug 30 16:10:58 2018
$end
$timescale 1ns $end
$scope module top $end
$var wire 1 $ clk $end
$scope module t $end
$var wire 1 $ clk $end
$var wire 32 # cyc [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
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b00000000000000000000000000110010 #
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b00000000000000000000000000110011 #
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b00000000000000000000000000110100 #
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b00000000000000000000000000110101 #
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b00000000000000000000000000110110 #
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b00000000000000000000000000110111 #
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b00000000000000000000000000111000 #
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b00000000000000000000000000111001 #
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b00000000000000000000000000111010 #
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b00000000000000000000000000111100 #
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b00000000000000000000000000111101 #
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b00000000000000000000000000111110 #
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b00000000000000000000000000111111 #
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b00000000000000000000000001000000 #
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b00000000000000000000000001000001 #
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b00000000000000000000000001000011 #
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b00000000000000000000000001010010 #
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b00000000000000000000000001010011 #
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b00000000000000000000000001010100 #
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0$