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39 lines
888 B
Verilog
39 lines
888 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2016 by Wilson Snyder.
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module t (clk);
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input clk;
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typedef struct packed {
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logic [2:0] _foo;
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logic [2:0] _bar;
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} struct_t;
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logic [2:0] meh;
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struct_t param;
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localparam integer twentyone = 21;
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// verilator lint_off WIDTH
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assign param = '{
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_foo: twentyone % 8 + 1,
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_bar: (twentyone / 8) + 1
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};
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assign meh = twentyone % 8 + 1;
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// verilator lint_on WIDTH
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$display("param: %d, %d, %b, %d", param._foo, param._bar, param, meh);
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`endif
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if (param._foo != 6) $stop;
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if (param._bar != 3) $stop;
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if (param != 6'b110011) $stop;
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if (meh != 6) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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