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42 lines
1.1 KiB
Verilog
42 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// A test case for parameterized module.
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//
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// When a module is instantiatied with parameter, there will be two modules in
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// the tree and eventually one will be removed after param and deadifyModules.
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//
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// This test is to check that the removal of dead module will not cause
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// compilation error. Possible error was/is seen as:
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//
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// pure virtual method called
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// terminate called without an active exception
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// %Error: Verilator aborted. Consider trying --debug --gdbbt
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jie Xu.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [71:0] ctrl;
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wire [7:0] cl; // this line is added
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memory #(.words(72)) i_memory (.clk (clk));
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assign ctrl = i_memory.mem[0];
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assign cl = i_memory.mem[0][7:0]; // and this line
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endmodule
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// memory module, which is used with parameter
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module memory (clk);
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input clk;
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parameter words = 16384, bits = 72;
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reg [bits-1 :0] mem[words-1 : 0];
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endmodule
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