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20 lines
362 B
Verilog
20 lines
362 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module m #(parameter int Foo);
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endmodule
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module t (/*AUTOARG*/);
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m #(10) foo();
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initial begin
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if (foo.Foo != 10) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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