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47 lines
1.4 KiB
Verilog
47 lines
1.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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i65, j65, i33, j33, i30, j30, q65, r65, q33, r33, q30, r30, w65, x65, w33,
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x33, w30, x30,
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// Inputs
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a, a40, a70
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);
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input [3:0] a;
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input [39:0] a40;
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input [69:0] a70;
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// -- Verilator 621c515 creates code that uses the undeclared function VL_POW_WWI()
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// verilator lint_off WIDTH
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output [3:0] i65 = 65'd3 ** a; // WWI
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output [3:0] j65 = a ** 65'd3; // IIW
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output [3:0] i33 = 33'd3 ** a; // QQI
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output [3:0] j33 = a ** 33'd3; // IIQ
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output [3:0] i30 = 30'd3 ** a; // III
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output [3:0] j30 = a ** 30'd3; // III
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output [39:0] q65 = 65'd3 ** a40; // WWQ
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output [39:0] r65 = a40 ** 65'd3; // WWQ
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output [39:0] q33 = 33'd3 ** a40; // QQQ
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output [39:0] r33 = a40 ** 33'd3; // QQQ
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output [39:0] q30 = 30'd3 ** a40; // QQI
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output [39:0] r30 = a40 ** 30'd3; // QQI
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output [69:0] w65 = 65'd3 ** a70; // WWW
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output [69:0] x65 = a70 ** 65'd3; // WWW
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output [69:0] w33 = 33'd3 ** a70; // WWW
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output [69:0] x33 = a70 ** 33'd3; // WWW
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output [69:0] w30 = 30'd3 ** a70; // WWW
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output [69:0] x30 = a70 ** 30'd3; // WWW
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// verilator lint_on WIDTH
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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