verilator/test_regress/t/t_lint_mod_paren_bad.v
2018-05-09 18:32:12 -04:00

19 lines
284 B
Verilog

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Wilson Snyder.
// Should have been:
//module t #(
module t
(
FOO=1
) (
output bar
);
assign bar = FOO;
endmodule