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51 lines
1.0 KiB
Verilog
51 lines
1.0 KiB
Verilog
// DESCRIPTION:tor:ilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [31:0] o;
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wire [31:0] oe;
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Test test (/*AUTOINST*/
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// Outputs
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.o (o[31:0]),
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.oe (oe[31:0]));
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// Test loop
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always @ (posedge clk) begin
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if (o !== 32'h00000001) $stop;
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if (oe !== 32'h00000001) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module subimp(o,oe);
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output [31:0] o;
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assign o = 32'h12345679;
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output [31:0] oe;
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assign oe = 32'hab345679;
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endmodule
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module Test(o,oe);
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output [31:0] o;
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output [31:0] oe;
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wire [31:0] xe;
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assign xe[31:1] = 0;
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// verilator lint_off IMPLICIT
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// verilator lint_off WIDTH
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subimp subimp(x, // x is implicit and one bit
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xe[0]); // xe explicit one bit
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assign o = x;
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assign oe = xe;
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// verilator lint_on WIDTH
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// verilator lint_on IMPLICIT
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endmodule
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