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34 lines
754 B
Verilog
34 lines
754 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2009 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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parameter integer BLKS = 3;
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generate
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for (genvar blkIdx=0; blkIdx < BLKS; blkIdx=blkIdx+1 ) begin : slice
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import "DPI-C" context function void dpi_genvarTest ();
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initial begin
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dpi_genvarTest();
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$display("slice = %0d : %m", blkIdx);
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end
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end
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endgenerate
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always @ (posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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