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28 lines
905 B
Verilog
28 lines
905 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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`timescale 1ns/1ns
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module t;
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initial begin
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// Display formatting
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$write; // Check missing arguments work
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$write("default: [%0t] 0t time [%t] No0 time\n",$time,$time);
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`ifndef verilator // Unsupported
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$timeformat(-9, 0, "", 0);
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$write("-9,0,,0: [%0t] 0t time [%t] No0 time\n",$time,$time);
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$timeformat(-9, 0, "", 10);
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$write("-9,0,,10: [%0t] 0t time [%t] No0 time\n",$time,$time);
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$timeformat(-9, 0, "ns", 5);
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$write("-9,0,ns,5: [%0t] 0t time [%t] No0 time\n",$time,$time);
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$timeformat(-9, 3, "ns", 8);
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$write("-9,3,ns,8: [%0t] 0t time [%t] No0 time\n",$time,$time);
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`endif
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$write("\n");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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