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102 lines
1.7 KiB
Verilog
102 lines
1.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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//
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/* verilator lint_off LITENDIAN */
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module some_module (
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input wrclk
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);
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logic [ 1 : 0 ] some_state;
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logic [1:0] some_other_state;
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always @(posedge wrclk) begin
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case (some_state)
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2'b11:
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if (some_other_state == 0)
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some_state <= 2'b00;
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default:
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$display ("This is a display statement");
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endcase
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if (wrclk)
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some_other_state <= 0;
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end
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endmodule
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`define BROKEN
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module t1(
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input [-12:-9] i_clks,
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input i_clk0,
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input i_clk1
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);
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some_module
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some_module
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(
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`ifdef BROKEN
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.wrclk (i_clks[-12])
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`else
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.wrclk (i_clk1)
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`endif
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);
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endmodule
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module t2(
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input [2:0] i_clks,
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input i_clk0,
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input i_clk1,
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input i_clk2,
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input i_data
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);
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logic [-12:-9] the_clks;
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logic data_q;
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assign the_clks[-12] = i_clk1;
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assign the_clks[-11] = i_clk2;
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assign the_clks[-10] = i_clk1;
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assign the_clks[-9] = i_clk0;
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always @(posedge i_clk0) begin
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data_q <= i_data;
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end
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t1 t1
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(
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.i_clks (the_clks),
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.i_clk0 (i_clk0),
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.i_clk1 (i_clk1)
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);
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endmodule
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module t(
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input clk0 /*verilator clocker*/,
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input clk1 /*verilator clocker*/,
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input clk2 /*verilator clocker*/,
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input data_in
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);
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logic [2:0] clks;
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assign clks = {1'b0, clk1, clk0};
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t2
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t2
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(
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.i_clks (clks),
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.i_clk0 (clk0),
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.i_clk1 (clk1),
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.i_clk2 (clk2),
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.i_data (data_in)
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);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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