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38 lines
775 B
Systemverilog
38 lines
775 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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function bit check_string(string s);
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if (s inside {"RW", "WO"})
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return 1'b1;
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return 1'b0;
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endfunction
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function bit check_double(real d);
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if (d inside {0.0, 2.5})
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return 1'b1;
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return 1'b0;
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endfunction
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module t();
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initial begin
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if (!check_string("WO"))
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$stop;
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if (!check_string("RW"))
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$stop;
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if (check_string("ABC"))
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$stop;
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if (!check_double(0.0))
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$stop;
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if (!check_double(2.5))
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$stop;
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if (check_double(1.0))
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$stop;
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$display("*-* All Finished *-*");
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$finish;
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end
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endmodule
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