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10 lines
478 B
Plaintext
10 lines
478 B
Plaintext
%Error-CONTASSREG: t/t_wire_beh_bad.v:11: Continuous assignment to reg, perhaps intended wire (IEEE 2005 6.1; Verilog only, legal in SV): 'r'
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: ... In instance t
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assign r = 1'b1;
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^
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%Error-PROCASSWIRE: t/t_wire_beh_bad.v:12: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
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: ... In instance t
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always @ (r) w = 1'b0;
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^
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%Error: Exiting due to
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