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30 lines
500 B
Systemverilog
30 lines
500 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2017 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface dummy_if ();
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logic sig_udrv;
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logic sig_uusd;
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endinterface: dummy_if
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module sub
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(
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dummy_if dummy
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);
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assign dummy.sig_uusd = 1'b0 | dummy.sig_udrv;
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endmodule
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module t (/*AUTOARG*/);
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dummy_if dummy ();
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sub sub
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(.dummy(dummy)
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);
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endmodule
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