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26 lines
446 B
Systemverilog
26 lines
446 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Chandan Egbert.
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// SPDX-License-Identifier: CC0-1.0
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module sub();
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endmodule
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module t(input logic a, input logic b,
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output logic x, output logic y);
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always_comb begin
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integer i;
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x = a;
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end
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sub u0();
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always_comb begin
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integer j;
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y = b;
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end
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endmodule
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