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verilator/test_regress/t/t_exit.v
2020-11-10 22:49:48 -05:00

13 lines
352 B
Systemverilog

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
program t(/*AUTOARG*/);
initial begin
$write("*-* All Finished *-*\n");
$exit; // Must be in program block
end
endprogram