verilator/test_regress/t/t_assert_unique_case_bad.out
Yutetsu TAKATSUKASA 65b632a7dd
Improve assertion for unique case (#4892)
- Use parallel_case, unique, and unique0 in error message
- Distinguish multiple match and no match
- Show the case value that triggers the assertion
2024-02-13 21:53:32 +09:00

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[90] %Error: t_assert_unique_case_bad.v:36: Assertion failed in top.t: unique case, but multiple matches found for '12'h388'
%Error: t/t_assert_unique_case_bad.v:36: Verilog $stop
Aborting...