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73 lines
2.3 KiB
Systemverilog
73 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Outputs
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i299,
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// Inputs
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i190, i191, i192, i193, i194, i195, i196, i197, i198, i199, i200, i201, i202,
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i203, i204, i205, i182, i183, i184, i185, i186, i187, i188, i189, i206, i282,
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i284, i286, i287, i289, i290, i294, i34, i288, i31, i296, i37, i38
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);
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input [3:0] i190;
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input [3:0] i191;
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input [3:0] i192;
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input [3:0] i193;
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input [3:0] i194;
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input [3:0] i195;
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input [3:0] i196;
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input [3:0] i197;
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input [3:0] i198;
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input [3:0] i199;
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input [3:0] i200;
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input [3:0] i201;
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input [3:0] i202;
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input [3:0] i203;
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input [3:0] i204;
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input [3:0] i205;
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input [3:0] i182;
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input [3:0] i183;
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input [3:0] i184;
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input [3:0] i185;
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input [3:0] i186;
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input [3:0] i187;
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input [3:0] i188;
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input [3:0] i189;
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input [3:0] i206;
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input [3:0] i282;
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input [3:0] i284;
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input [3:0] i286;
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input [3:0] i287;
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input [3:0] i289;
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input [3:0] i290;
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input [3:0] i294;
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input [3:0] i34;
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input [3:0] i288;
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input [3:0] i31;
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input [3:0] i296;
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input [3:0] i37;
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input [3:0] i38;
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output [3:0] i299;
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assign i299 = { i296[2:0] | i31[3:1] | i282[3:1] | i284[3:1] | i34[3:1]
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| i286[3:1] | i287[3:1] | i37[3:1] | i38[3:1]
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| i288[3:1] | i289[3:1] | i290[3:1] | i182[3:1]
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| i183[3:1] | i184[3:1] | i185[3:1] | i186[3:1]
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| i187[3:1] | i188[3:1] | i189[3:1] | i190[3:1]
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| i191[3:1] | i192[3:1] | i193[3:1] | i194[3:1]
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| i195[3:1] | i196[3:1] | i197[3:1] | i198[3:1]
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| i199[3:1] | i200[3:1] | i201[3:1] | i202[3:1]
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| i203[3:1] | i204[3:1] | i205[3:1] | i206[3:1]
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,
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i294[0] | i289[0] | i290[0] | i182[0] | i183[0]
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| i184[0] | i185[0] | i186[0] | i187[0] | i188[0]
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| i189[0] | i190[0] | i191[0] | i192[0] | i193[0]
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| i194[0] | i195[0] | i196[0] | i197[0] | i198[0]
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| i199[0] | i200[0] | i201[0] | i202[0] | i203[0]
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| i204[0] | i205[0] | i206[0] };
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endmodule
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