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32 lines
600 B
Verilog
32 lines
600 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t (/*AUTOARG*/);
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reg signed [2:0] negcnt;
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integer times;
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initial begin
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times = 0;
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repeat (1) begin
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repeat (0) $stop;
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repeat (-1) $stop;
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negcnt = 'sb111;
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repeat (negcnt) $stop;
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repeat (5) begin
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repeat (2) begin
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times = times + 1;
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end
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end
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end
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if (times != 10) $stop;
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//
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forever begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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