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125 lines
3.4 KiB
Verilog
125 lines
3.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2004 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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ign, ign2, ign3,
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// Inputs
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clk
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);
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input clk;
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output [31:0] ign;
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output [3:0] ign2;
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output [11:0] ign3;
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parameter [95:0] P6 = 6;
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localparam P64 = (1 << P6);
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// verilator lint_off WIDTH
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localparam [4:0] PBIG23 = 1'b1 << ~73'b0;
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localparam [3:0] PBIG29 = 4'b1 << 33'h100000000;
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// verilator lint_on WIDTH
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reg [31:0] right;
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reg [31:0] left;
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reg [P64-1:0] qright;
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reg [P64-1:0] qleft;
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reg [31:0] amt;
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assign ign = {31'h0, clk} >>> 4'bx; // bug760
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assign ign2 = {amt[1:0] >> {22{amt[5:2]}}, amt[1:0] << (0 <<< amt[5:2])}; // bug1174
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assign ign3 = {amt[1:0] >> {22{amt[5:2]}},
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amt[1:0] >> {11{amt[5:2]}},
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$signed(amt[1:0]) >>> {22{amt[5:2]}},
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$signed(amt[1:0]) >>> {11{amt[5:2]}},
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amt[1:0] << {22{amt[5:2]}},
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amt[1:0] << {11{amt[5:2]}}};
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always @* begin
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right = 32'h819b018a >> amt;
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left = 32'h819b018a << amt;
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qright = 64'hf784bf8f_12734089 >> amt;
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qleft = 64'hf784bf8f_12734089 >> amt;
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end
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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`ifdef TEST_VERBOSE
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$write("%d %x %x %x %x\n", cyc, left, right, qleft, qright);
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`endif
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if (cyc==1) begin
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amt <= 32'd0;
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if (P64 != 64) $stop;
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if (5'b10110>>2 != 5'b00101) $stop;
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if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness
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if (5'b10110<<2 != 5'b11000) $stop;
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if (5'b10110<<<2 != 5'b11000) $stop;
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if (5'sb10110>>2 != 5'sb00101) $stop;
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if (5'sb10110>>>2 != 5'sb11101) $stop;
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if (5'sb10110<<2 != 5'sb11000) $stop;
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if (5'sb10110<<<2 != 5'sb11000) $stop;
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// Allow >64 bit shifts if the shift amount is a constant
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if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop;
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end
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if (cyc==2) begin
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amt <= 32'd28;
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if (left != 32'h819b018a) $stop;
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if (right != 32'h819b018a) $stop;
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if (qleft != 64'hf784bf8f_12734089) $stop;
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if (qright != 64'hf784bf8f_12734089) $stop;
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end
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if (cyc==3) begin
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amt <= 32'd31;
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if (left != 32'ha0000000) $stop;
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if (right != 32'h8) $stop;
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if (qleft != 64'h0000000f784bf8f1) $stop;
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if (qright != 64'h0000000f784bf8f1) $stop;
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end
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if (cyc==4) begin
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amt <= 32'd32;
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if (left != 32'h0) $stop;
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if (right != 32'h1) $stop;
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if (qleft != 64'h00000001ef097f1e) $stop;
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if (qright != 64'h00000001ef097f1e) $stop;
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end
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if (cyc==5) begin
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amt <= 32'd33;
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if (left != 32'h0) $stop;
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if (right != 32'h0) $stop;
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if (qleft != 64'h00000000f784bf8f) $stop;
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if (qright != 64'h00000000f784bf8f) $stop;
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end
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if (cyc==6) begin
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amt <= 32'd64;
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if (left != 32'h0) $stop;
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if (right != 32'h0) $stop;
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if (qleft != 64'h000000007bc25fc7) $stop;
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if (qright != 64'h000000007bc25fc7) $stop;
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end
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if (cyc==7) begin
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amt <= 32'd128;
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if (left != 32'h0) $stop;
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if (right != 32'h0) $stop;
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if (qleft != 64'h0) $stop;
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if (qright != 64'h0) $stop;
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end
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if (cyc==8) begin
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if (left != 32'h0) $stop;
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if (right != 32'h0) $stop;
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if (qleft != 64'h0) $stop;
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if (qright != 64'h0) $stop;
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end
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if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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