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20 lines
304 B
Verilog
20 lines
304 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2016 by Wilson Snyder.
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module t
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(
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input wire rst
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);
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integer q;
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always @(*)
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if (rst)
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assign q = 0;
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else
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deassign q;
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endmodule
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