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44 lines
741 B
Verilog
44 lines
741 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=1;
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counter_io c_data();
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counter_ansi c1 (.clk, .*);
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counter_ansi c2 (.clk, .c_data);
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==20) begin
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if (c_data.value != 12345) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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interface counter_io;
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integer value;
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endinterface
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module counter_ansi
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(
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input clk,
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counter_io c_data
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);
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always_ff @ (posedge clk) begin
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c_data.value <= 12345;
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end
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endmodule : counter_ansi
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