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32 lines
566 B
Verilog
32 lines
566 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc = 0;
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integer a;
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integer b;
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initial begin
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a <= 22;
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b <= 33;
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end
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==99) begin
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if (a != 22) $stop;
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if (b != 33) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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