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33 lines
765 B
Verilog
33 lines
765 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2018 by Julien Margetts.
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module t #(parameter sz = 4096)
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(
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input wire clk,
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output reg [tdw(sz)-1:0] data
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);
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// bug1330
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function integer clog2(input integer value);
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integer tmp;
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tmp = value-1;
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clog2 = 0;
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for (clog2=0; (tmp>0) && (clog2<32); clog2=clog2+1)
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tmp = tmp>>1;
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endfunction
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function integer tdw(input integer sz);
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tdw = clog2(sz);
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endfunction
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integer b;
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always @(posedge clk)
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for (b=0; b<tdw(sz); b=b+1)
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if ((data[b] === 1'bx))
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$display("WARNING: %1t Writing X's to tag RAM [%m]", $time);
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endmodule
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