mirror of
https://github.com/verilator/verilator.git
synced 2025-01-07 15:17:36 +00:00
12 lines
259 B
Verilog
12 lines
259 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2008 by Wilson Snyder.
|
|
|
|
module t;
|
|
initial begin
|
|
$write("*-* All Finished *-*\n");
|
|
$finish;
|
|
end
|
|
endmodule
|