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79 lines
1.7 KiB
Verilog
79 lines
1.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003-2007 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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/*verilator public_module*/
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input clk;
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// No verilator_public needed, because it's outside the "" in the $c statement
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reg [7:0] cyc; initial cyc=0;
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reg c_worked;
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reg [8:0] c_wider;
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wire one = 1'b1;
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always @ (posedge clk) begin
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cyc <= cyc+8'd1;
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// coverage testing
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if (one) begin end
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if (!one) begin end
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if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line
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if (cyc == 8'd1) begin
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c_worked <= 0;
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end
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if (cyc == 8'd2) begin
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`ifdef VERILATOR
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$c("VL_PRINTF(\"Calling $c, calling $c...\\n\");");
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$c("VL_PRINTF(\"Cyc=%d\\n\",",cyc,");");
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c_worked <= $c("my_function()");
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c_wider <= $c9("0x10");
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`else
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c_worked <= 1'b1;
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c_wider <= 9'h10;
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`endif
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end
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if (cyc == 8'd3) begin
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if (c_worked !== 1'b1) $stop;
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if (c_wider !== 9'h10) $stop;
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$finish;
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end
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end
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`ifdef verilator
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`systemc_header
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#define DID_INT_HEADER 1
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`systemc_interface
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#ifndef DID_INT_HEADER
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#error "`systemc_header didn't work"
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#endif
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bool m_did_ctor;
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vluint32_t my_function() {
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if (!m_did_ctor) vl_fatal(__FILE__,__LINE__,__FILE__,"`systemc_ctor didn't work");
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return 1;
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}
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`systemc_imp_header
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#define DID_IMP_HEADER 1
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`systemc_implementation
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#ifndef DID_IMP_HEADER
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#error "`systemc_imp_header didn't work"
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#endif
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`systemc_ctor
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m_did_ctor = 1;
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`systemc_dtor
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printf("In systemc_dtor\n");
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printf("*-* All Finished *-*\n");
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`verilog
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// Test verilator comment after a endif
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`endif // verilator
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endmodule
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