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67 lines
1.6 KiB
Verilog
67 lines
1.6 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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reg out1;
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reg [4:0] out2;
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sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n",$time, cyc, crc, sum, crc[3:0], out1,out2);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
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if (cyc==0) begin
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// Setup
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crc <= 64'h00000000_00000097;
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sum <= 64'h0;
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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`define EXPECTED_SUM 64'h10204fa5567c8a4b
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub (/*AUTOARG*/
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// Outputs
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out1, out2,
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// Inputs
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in
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);
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input [23:0] in;
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output reg out1;
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output reg [4:0] out2;
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always @* begin
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case (in[3:0]) inside
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default: {out1,out2} = {1'b0,5'h0F}; // Note not last item
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4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01};
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4'h4: {out1,out2} = {1'b1,5'h04};
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[4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match
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4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08};
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[4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C};
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endcase
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end
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endmodule
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