mirror of
https://github.com/verilator/verilator.git
synced 2025-01-07 15:17:36 +00:00
19 lines
386 B
Verilog
19 lines
386 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2005 by Wilson Snyder.
|
|
|
|
module t (/*AUTOARG*/
|
|
// Inputs
|
|
value
|
|
);
|
|
input [3:0] value;
|
|
always @ (/*AS*/value) begin
|
|
case (value)
|
|
default: $stop;
|
|
4'd0000: $stop;
|
|
default: $stop;
|
|
endcase
|
|
end
|
|
endmodule
|