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48 lines
1.1 KiB
Systemverilog
48 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package pkga;
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int pvar;
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class MyClass;
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int member;
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function int getpvar(); return pvar; endfunction
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endclass
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endpackage
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package pkgb;
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int pvar;
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class MyClass;
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int member;
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function int getpvar(); return pvar; endfunction
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function int getavar(); return pkga::pvar; endfunction
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endclass
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endpackage
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module t (/*AUTOARG*/);
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initial begin
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pkga::MyClass a;
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pkgb::MyClass b;
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pkga::pvar = 100;
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pkgb::pvar = 200;
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if (pkga::pvar != 100) $stop;
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if (pkgb::pvar != 200) $stop;
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a = new;
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b = new;
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a.member = 10;
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b.member = 20;
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if (a.member != 10) $stop;
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if (b.member != 20) $stop;
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if (a.getpvar() != 100) $stop;
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if (b.getpvar() != 200) $stop;
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if (b.getavar() != 100) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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