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109 lines
2.5 KiB
Systemverilog
109 lines
2.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class c1;
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rand int c1_f;
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endclass
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class c2;
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rand int c2_f;
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endclass
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class Cls;
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rand int x;
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rand enum {
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ONE_Y,
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TWO_Y
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} y;
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virtual function int get_x();
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return x;
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endfunction
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endclass
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class SubA extends Cls;
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c1 e = new;
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rand enum {
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AMBIG,
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ONE_A,
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TWO_A
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} en;
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function c1 get_c();
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return e;
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endfunction
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function int op(int v);
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return v + 1;
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endfunction
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endclass
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class SubB extends Cls;
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int z;
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endclass
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class SubC extends SubB;
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c2 e = new;
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rand enum {
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AMBIG,
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ONE_B,
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TWO_B
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} en;
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SubA f = new;
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function c2 get_c();
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return e;
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endfunction
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function int op(int v);
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return v - 1;
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endfunction
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function int doit;
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// access ambiguous names so width complains if we miss something
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doit = 1;
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f.x = 4;
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x = 5;
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doit = f.randomize() with { x == local::x; };
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if (f.x != x) $stop;
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z = 6;
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doit &= f.randomize() with { x == z; };
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if (f.x != z) $stop;
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doit &= f.randomize() with { e.c1_f == local::e.c2_f; };
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doit &= f.randomize() with { get_x() == local::get_x(); };
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doit &= f.randomize() with { get_c().c1_f == local::get_c().c2_f; };
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doit &= f.randomize() with { (get_c).c1_f == (local::get_c).c2_f; };
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f.y = ONE_Y;
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y = TWO_Y;
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doit &= f.randomize() with { y == local::y; };
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if (f.y != y) $stop;
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f.en = SubA::ONE_A;
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doit &= f.randomize() with { en == AMBIG; };
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if (doit != 1) $stop;
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if (f.en != SubA::AMBIG) $stop;
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f.en = SubA::ONE_A;
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doit &= f.randomize() with { en == ONE_A; };
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doit &= f.randomize() with { local::en == local::AMBIG; };
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en = ONE_B;
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doit &= f.randomize() with { local::en == ONE_B; };
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doit &= f.randomize() with { x == local::op(op(0)); };
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if (f.x != 0) $stop;
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doit &= f.randomize() with { x == op(local::op(1)); };
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if (f.x != 1) $stop;
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doit &= f.randomize() with { x == local::op(op(local::op(op(0)))); };
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if (f.x != 0) $stop;
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doit &= f.randomize() with { x == op(local::op(op(local::op(1)))); };
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if (f.x != 1) $stop;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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SubC obj = new;
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initial begin
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if (obj.doit != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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