verilator/test_regress/t/t_preproc_psl_off.out
Wilson Snyder 79d305f3e8 Match Verilog-Perl: Remove preprocessor adding newlines before `line.
git-svn-id: file://localhost/svn/verilator/trunk/verilator@948 77ca24e4-aefa-0310-84f0-b9a241c72d87
2007-07-30 15:00:21 +00:00

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`line 1 "t/t_preproc_psl.v" 1
/*verilator metacomment preserved*/
/*verilator metacomment also_preserved*/
Hello in t_preproc_psl.v
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`line 59 "t/t_preproc_psl.v" 0
`psl
psl assert always sig!=90;
`verilog
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`line 73 "t/t_preproc_psl.v" 2