mirror of
https://github.com/verilator/verilator.git
synced 2025-04-09 14:12:39 +00:00
10 lines
269 B
Systemverilog
10 lines
269 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2019 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t (portwithoin);
|
|
input portwithin;
|
|
endmodule
|