mirror of
https://github.com/verilator/verilator.git
synced 2025-01-09 16:17:36 +00:00
18 lines
365 B
Verilog
18 lines
365 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2003 by Wilson Snyder.
|
|
|
|
module t;
|
|
|
|
reg [175:0] hex [15:0];
|
|
|
|
integer i;
|
|
|
|
initial begin
|
|
$readmemh("t/t_sys_readmem_bad_end.mem", hex, 0, 15);
|
|
$write("*-* All Finished *-*\n");
|
|
$finish;
|
|
end
|
|
endmodule
|