verilator/test_regress/t/t_lint_setout_bad_noinl.out
2019-07-14 21:42:03 -04:00

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%Error-PORTSHORT: t/t_lint_setout_bad.v:16: Output port is connected to a constant pin, electrical short
.cpu_if_timeout(1'b0)
^~~~~~~~~~~~~~
%Error: Exiting due to