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5b3717b369
This patch normalizes what the tests do before exiting. After this change each test should call final on the top module and explicitly free the top module object before exiting.
59 lines
1.3 KiB
C++
59 lines
1.3 KiB
C++
// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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#include <verilated.h>
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#include "Vt_dpi_vams.h"
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//======================================================================
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// clang-format off
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#if defined(VERILATOR)
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# include "Vt_dpi_vams__Dpi.h"
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#elif defined(VCS)
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# include "../vc_hdrs.h"
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#elif defined(CADENCE)
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# define NEED_EXTERNS
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#else
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# error "Unknown simulator for DPI test"
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#endif
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// clang-format on
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#ifdef NEED_EXTERNS
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extern "C" {
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extern void dpii_call(double in, double* outp);
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}
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#endif
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void dpii_call(double in, double* outp) { *outp = in + 0.1; }
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//======================================================================
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unsigned int main_time = 0;
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double sc_time_stamp() { return main_time; }
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VM_PREFIX* topp = nullptr;
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int main(int argc, char* argv[]) {
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topp = new VM_PREFIX;
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Verilated::debug(0);
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topp->in = 1.1;
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topp->eval();
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if (topp->out != 1.2) {
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VL_PRINTF("*-* All Finished *-*\n");
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topp->final();
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} else {
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vl_fatal(__FILE__, __LINE__, "top", "Unexpected results\n");
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}
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topp->final();
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VL_DO_DANGLING(delete topp, topp);
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return 0;
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}
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