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40 lines
1.3 KiB
Systemverilog
40 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2018 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// issue2895
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module t (/*AUTOARG*/);
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localparam string REG_X [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0",
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"t1", "t2", "s0/fp", "s1", "a0", "a1",
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"a2", "a3", "a4", "a5", "a6", "a7", "s2",
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"s3", "s4", "s5", "s6", "s7", "s8", "s9",
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"s10", "s11", "t3", "t4", "t5", "t6"};
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function automatic string reg_x (logic [4:0] r, bit abi=1'b0);
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reg_x = abi ? REG_X[r] : $sformatf("x%0d", r);
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endfunction
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// the issue is triggered by a second function containing a case statement
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function automatic string f2 (logic [4:0] r, bit abi=0);
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case (r)
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5'd0: f2 = $sformatf("nop");
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5'd1: f2 = $sformatf("reg %s", reg_x(r[4:0], abi));
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default: f2 = $sformatf("ILLEGAL");
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endcase
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endfunction
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initial begin
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for (int unsigned i = 0; i < 32; ++i) begin
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$display("REGX: %s", reg_x(i[4:0], 1'b1));
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end
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$display("OP: %s", f2(5'd7));
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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