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40 lines
800 B
Systemverilog
40 lines
800 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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int x = 1;
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endclass
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class Bar extends Foo;
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function new;
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x = 2;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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int sel_bit = 3;
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Bar bar = new;
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Foo foo = bar;
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Bar bars[] = new[4];
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$cast(bars[0], foo);
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if (bars[0].x != 2) $stop;
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$cast(bars[sel_bit[0]], foo);
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if (bars[1].x != 2) $stop;
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$cast(bars[bars[0].x], foo);
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if (bars[2].x != 2) $stop;
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$cast(bars[sel_bit[1:0]], foo);
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if (bars[3].x != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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