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https://github.com/verilator/verilator.git
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153 lines
3.7 KiB
Plaintext
153 lines
3.7 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$date Thu Oct 24 09:45:30 2019
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$end
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$timescale 1ns $end
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$scope module top $end
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$var wire 1 1 clk $end
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$scope module t $end
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$var wire 1 1 clk $end
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$var wire 32 $ cyc [31:0] $end
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$var wire 8 % cyc_copy [7:0] $end
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$var wire 1 # toggle $end
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$var wire 32 ) vlCoverageLineTrace_t_cover_line__44_if [31:0] $end
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$var wire 32 & vlCoverageLineTrace_t_cover_line__47_if [31:0] $end
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$var wire 32 ' vlCoverageLineTrace_t_cover_line__50_elsif [31:0] $end
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$var wire 32 ( vlCoverageLineTrace_t_cover_line__57_elsif [31:0] $end
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$scope module a1 $end
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$var wire 1 1 clk $end
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$var wire 1 # toggle $end
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$var wire 32 * vlCoverageLineTrace_t_cover_line__78_if [31:0] $end
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$upscope $end
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$scope module a2 $end
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$var wire 1 1 clk $end
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$var wire 1 # toggle $end
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$var wire 32 + vlCoverageLineTrace_t_cover_line__78_if [31:0] $end
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$upscope $end
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$scope module b1 $end
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$var wire 1 1 clk $end
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$var wire 1 # toggle $end
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$var wire 32 2 vlCoverageLineTrace_t_cover_line__101_if [31:0] $end
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$var wire 32 - vlCoverageLineTrace_t_cover_line__105_if [31:0] $end
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$upscope $end
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$scope module b2 $end
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$var wire 1 1 clk $end
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$var wire 1 # toggle $end
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$var wire 32 3 vlCoverageLineTrace_t_cover_line__101_if [31:0] $end
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$var wire 32 . vlCoverageLineTrace_t_cover_line__105_if [31:0] $end
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$upscope $end
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$scope module o1 $end
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$var wire 1 1 clk $end
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$var wire 1 # toggle $end
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$var wire 32 , vlCoverageLineTrace_t_cover_line__162_if [31:0] $end
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$upscope $end
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$scope module t1 $end
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$var wire 1 1 clk $end
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$var wire 1 # toggle $end
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$var wire 32 / vlCoverageLineTrace_t_cover_line__134_if [31:0] $end
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$var wire 32 0 vlCoverageLineTrace_t_cover_line__137_if [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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