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verilator/test_regress/t/t_display_esc_bad.v
2020-03-21 11:24:24 -04:00

12 lines
304 B
Systemverilog

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
initial begin
$display("\x\y\z"); // Illegal escapes
end
endmodule