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34 lines
613 B
Verilog
34 lines
613 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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package p3;
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typedef enum logic [2:0] {
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ZERO = 3'b0,
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ONE = 3'b1 } e3_t /*verilator public*/;
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endpackage
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package p62;
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typedef enum logic [62:0] {
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ZERO = '0,
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ALLONE = '1 } e62_t /*verilator public*/;
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endpackage
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module t (/*AUTOARG*/);
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enum integer {
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EI_A,
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EI_B,
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EI_C
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} m_state;
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initial begin
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m_state = EI_A;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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